FIG. 1 is a diagram illustrating a schematic configuration of a high-speed signal transfer system. As illustrated in FIG. 1, the signal transfer system includes a transmission circuit 1, a transfer line 2 and a reception circuit 3. In the transmission circuit 1, low-speed parallel data is converted into serial data in a multiplexer (MUX) 11 and the serial data is output to the transfer line 2 by a driver 12 having an output impedance the same as the characteristic impedance of the transfer line 2. The serial data is input to the reception circuit 3 via the transfer line 2. An input reception waveform received by the reception circuit 3 is deteriorated by the characteristics of the transfer line 2. Specifically, the high-frequency component is lost and the waveform is dulled.
Data to be transmitted is two-value data of “0's” and “1's” (or “−1” and “+1”) and when the degree of deterioration through the transfer line 2 is low, the input reception waveform for the serial data indicated by a string of “0's” and “1's” on the lower side is such that as illustrated in FIG. 2A. With this received signal waveform, it is possible to correctly reproduce the received data by setting a threshold level to a level indicated by the broken line and by determining the waveform with a comparator.
However, when the transfer line 2 is long or the frequency of the transmission data is very high, the degree of deterioration through the transfer line 2 is high and the input reception waveform for the serial data indicated by a string of “0's” and “1's” on the lower side is such that as illustrated in FIG. 2B. With such a received signal waveform, it is not possible to correctly reproduce received data by determining the waveform using only one comparator. In order to deal with this, the signal level is detected in accordance with a clock of the received data as illustrated in FIG. 2B and then the received data is reproduced correctly.
Because of this, as illustrated in FIG. 1, the reception circuit 3 samples the received signal (analog waveform) and digitizes the signal using an analog/digital converter (ADC) 31 arranged at the input part. An equalization circuit (EQ) 32 shapes the waveform (equalization processing) so as to compensate for the deterioration of waveform through the transfer line. The received data that is shaped is determined to be “0” or “1” and the determination result is converted from serial data into parallel data by a decision latch/demultiplexer (D/L DMUX) 33. A clock signal is necessary for sampling in the ADC 31 and processing in the equalization circuit 32. A clock recovery unit (CRU) 34 reproduces a data clock from the received data output from the equalization circuit 32. In the circuits to be explained below, the CRU 34 is also provided, however, an explanation is not given for the sake of simplification and it is not illustrated schematically.
FIGS. 3A and 3B are diagrams illustrating a configuration of an embodiment of the equalization circuit 32 called a decision feedback equalizer (DFE). FIG. 3A illustrates a conceptual diagram and FIG. 3B illustrates a specific circuit configuration. If a transfer function of the transfer line 2 is assumed to be H (z) as illustrated in FIG. 3A, adjustment is made so that the transfer function of a DFE 37 is 1−H (z). One sample received signal is H (z) and if the output 1−H (z) of the DFE 37 is added to a received signal H (z) by an adder 35, a signal without deterioration is output as a result and this output is determined by a comparator 36. Due to this, transmission data dn may be received correctly. Specifically, in order to sequentially correct the influence of the previous sample data, the sample data ahead by one sample is delayed by one sampling period and the sample data ahead by two samples is delayed by two sampling periods, and in this manner, the sample data is delayed sequentially up to that ahead by a certain number of samples and the delayed data is multiplied by a coefficient in accordance with the degree of influence and added to input data.
As illustrated in FIG. 3B, the equalization circuit 32 includes the DFE 37 having a plurality of multipliers hn0 to hnm, a plurality of the adders 35, the comparator 36, a switch 38 that switches between feedback of data having been subjected to equalization processing and feedback of training data, a comparator 39 that binarizes data to be fed back, a plurality of delay units 40 that generate data to be applied to hn1 to hnm after delaying the binarized feedback data, a subtracter 41 that calculates a difference between the data having been subjected to equalization processing and the binarized feedback data and generates an amount of error en, and a coefficient update part (e.c. LMS (Least-mean-square)) 42 that updates the coefficients of the multipliers hn0 to hnm so that the amount of error is small based on the amount of error en. The multiplier hn0 multiplies the data output from the ADC 31 by a certain coefficient and outputs the data and the multipliers hn1 to hnm multiply the previous sample data that is delayed by a certain coefficient and output the data, and the data is added by the adder 35.
H (z) is a z function and because of the limitations of hardware, normally, the terms beyond a certain finite term are truncated. As the coefficients of the multipliers hn0 to hnm, the values acquired by applying the LMS algorithm are set here; however, there may be a case where fixed values are set in advance. The coefficients of the multiplier represent the frequency characteristic of the transfer line. The amount of error, which is an input to the coefficient update part 42, is an error from an ideal waveform that remains even after the waveform shaping using the coefficients. The magnitude of the error represents the quality of the shaped waveform.
The equalization circuit is described in, for example, Japanese Laid-open Patent Publication No. 2000-224080, and therefore, no further explanation is provided.
There are various types for the ADC, however, an ADC that may be used generally in high-speed signal transfer as high as Giga bits/sec is limited to a flash type at present. In a flash type ADC, between a high-side reference potential and a low-side reference potential, a resistor string (ladder resistor) is provided and a divided potential, which is the reference potential divided, is generated at the connection node. Each of a plurality of comparators compares a voltage of an input signal (input voltage) with the divided potentials, respectively. When the input voltage is smaller than a certain divided potential, the output of the comparators located on the upper side of the comparator that makes a comparison with the divided potential is “0” and the comparators located on the lower side of the comparator, including the comparator, is “1”, which is a so-called thermometer manner, and when the outputs of the plurality of comparators are encoded by an encoder, a digital output in the binary form in accordance with the level of the input voltage is obtained. For an N-bit ADC without an interpolation technique, (2N−1) comparators are required.
The input/output characteristics of an ADC are not linear but nonlinear because of variations in the size of its circuit constituent component or in threshold voltage Vth. FIG. 4 is a diagram explaining the nonlinearity of the ADC. When the ADC exhibits the characteristic illustrated by the stepwise solid line, the input/output characteristics are illustrated by the broken line, different from the input/output characteristics illustrated by the alternate long and short dash line.
In order for the equalization circuit to perform equalization processing to correctly receive data, it is necessary for the input/output characteristics of the ADC to include linearity.
One of the reasons for that the input/output characteristics of the ADC include nonlinearity is the offset of the input part. Because of this, the ADC circuit in the conventional example incorporates an offset voltage generation circuit and an offset cancel circuit configured by a switch that operates with a clock in order to alleviate the degree of nonlinearity.
Japanese Laid-open Patent Publication No. 2003-536342 describes a method of correcting nonlinearity by providing a conversion table used to convert an output of an ADC and creating the conversion table based on the already-known calibration signal to be input from a reference signal input terminal.